The present invention relates to a boundary-scan circuit, and more particularly to a boundary-scan register circuit that provides both an input and an output function to a bidirectional pin of an electronic device.
The semiconductor industry has adopted IEEE Std. 1149.1 (1990), which is hereby incorporated by reference, in order to provide a standard test architecture. The intent of this standard is to provide compatibility of test control and data signals between devices from different manufacturers in much the same way that logic compatibility within a logic family exists. The standard test architecture will allow the development of standard tests and standard test development techniques.
The standard architecture has provisions for numerous types of testing. Boundary-scan testing and built-in-self-test (BIST) testing are two of the commonly used provisions.
To provide boundary-scan testing, a boundary-scan circuit arrangement is included in an electronic device between the connection pins and the remainder of the unit that it is a part of. These connection pins, or simply pins, may connect to inputs, outputs or inputs/outputs of the electronic device, which means the boundary-scan circuits may be input, output or bidirectional in nature. Some implementations of input and of output boundary-scan circuits are shown in the standard. The input circuit and the output circuit each use approximately four sub-circuits to provide the functions necessary for the input or the output boundary-scan circuit. The standard also shows two implementations for bidirectional boundary-scan circuits. The first of the bidirectional circuits is shown in FIG. 1, which is a general description of a bidirectional boundary scan circuit. FIGS. 2A and 2B form one realization of FIG. 1 using the input boundary-scan circuit and the output boundary-scan circuit most often used in the standard. FIGS. 3A and 3B together show a second implementation of a bidirectional boundary-scan circuit.
The bidirectional boundary-scan circuit shown in FIGS. 2A and 2B has twelve sub-circuit functions: six type D flip-flops (DFF) and six two-to-one multiplexers (2-to-1 MUXs). The bidirectional boundary-scan circuit shown in FIGS. 3A and 3B likewise has twelve sub-circuit functions: four DFF, six 2-to-1 MUXs and two AND gates. Considering that bidirectional pins of an electronic device often come in multiples of eight, for example an input/output data bus connection, the amount of area taken up by bidirectional boundary-scan circuits can become substantial. This causes the designer of the electronic device to consider limiting the extent that boundary-scan is included on the electronic device because of the extra costs involved.
Thus, it is an object of the present invention to provide a bidirectional boundary scan circuit that requires fewer sub-circuit functions and less area of the semiconductor device per circuit.
It is another object of the present invention to provide a bidirectional boundary scan circuit that requires fewer sub-circuit functions and also provides a bidirectional BIST capability.